1. Field of the Invention
This invention relates to an amplifier for driving a load, and, in particular, it relates to an amplifier that is high-speed, of high output power and stable in varying load.
2. Background Arts
There are cases in which the necessity arises for high-speed and high-electric-power driving of circuit elements that serve as loads in various types of electrical and electronic devices such as circuit element testers. In such cases, push-pull amplifiers, complementary amplifiers or combinations thereof are frequently used as the high output amplifiers which are the final stages in which such driving is performed.
A push-pull amplifier that is constructed using bipolar transistors is described in Japanese Laid-open Publication JP1996-32367A. This push-pull amplifier could show a lower crossover distortion without increasing an idling current (through current) in the output stage and high efficiency. Because any part of the circuit is not cut off there is not accumulation of minority carriers, which may be a problem with bipolar transistors, then, higher speed and broader bands can be achieved.
FIG. 1 shows high output amplifier 10 based on a conventional technology similar to that of the aforementioned push-pull amplifier. The high output amplifier 10 is constructed of circuit elements arranged between supply voltages VD and VS. Load voltage V2, which is essentially equal to control voltage V1 that has been input into terminal 1, is output to terminal 2. Transistors Q1 and Q2 are biased by a series of bias circuits comprised of resistances R1 and R2 and diodes D1 and D2. Terminal 1 is connected to a common connecting point of diodes D1 and D2 so that control voltage Vc is input into the control terminals (bases) of transistors Q1 and Q2 respectively. Transistors Q1 and Q2 are, respectively, NPN and PNP transistors and their emitters are connected to terminal 2 through resistance R4 or resistance R5. Transistors Q1 and Q2 act as a complementary buffer. The respective collectors of transistors Q1 and Q2 are connected to supply voltages VD and VS through resistances R3 and R6 respectively and are also connected to the non-inverting input terminals of amplifiers A1 and A2. Outputs of amplifiers A1 and A2 are connected to the gates of respective transistors Q3 and Q4 and the inverting input terminals of amplifiers A1 and A2 are connected to the sources of the respective transistors Q3 and Q4. Further, the sources of transistors Q3 and Q4, which are field effect transistors (FET), are connected to the respective supply voltages VD and VS through resistances R7 and R8. The drains of transistors Q3 and Q4 are both connected to terminal 2. Load LD is connected to terminal 2. Load LD may generally be passive or active.
First, we shall consider this amplifier 10 by ignoring transistors Q3 and Q4. Transistors Q1 and Q2 act in response to control voltage Vc so as to output voltage V2, which is close to control voltage Vc, to load LD. However, when load LD is heavy (when load current 12 is high such as in the case of low load impedance), load voltage V2 does not follow control voltage Vc. At a setting at which load current I2 flows out to load LD, transistor Q1 approaches saturation due to an increase of load current I2 and transistor Q2 is cut off. However, load current I2 also flows to resistance R3 and voltage is generated across resistance R3. Amplifier A1 controls the gate voltage of transistor Q3 so that the voltage applied across resistance R3 and the voltage applied across resistance R7 become equal to each other. Current of a value obtained by dividing the value of voltage across the resistance R3 by the value of resistance R7 is supplied from the drain of transistor Q3 to the terminal 2. When this occurs, the current flowing through transistor Q1 is decreased and the voltage across resistance R3 is also decreased. By means of this negative feedback, high output amplifier 10 is stabilized when the voltage applied across resistance R3 reaches a certain level. Similar stabilization also occurs at a setting at which load current I2 flows in from load LD. Similar actions are also effected on the sides of transistors Q2 and Q4. Consequently, there are two feedback loops of electrical signals. In one loop the signal is fed back from terminal 2 to terminal 2 via the transistor Q1, amplifier A1 and transistor Q3 and in another loop the signal is fed back from terminal 2 to terminal 2 via the transistor Q2, amplifier A2 and transistor Q4. So that any electrical signal on terminal 2, input to or generated at terminal 2, which may be a change in voltage or current through originated from a change in voltage, current or circuit parameter, is fed back negatively.
In the amplifier 10 of FIG. 1, as indicated above, we have described transistors Q3 and Q4 as field effect transistors for high power use. However, they may also be bipolar transistors for high power use and switching-mode power sources. Further, field effect transistors or amplifiers may be used in place of transistors Q1 and Q2. However, transistors Q1 and Q2 are generally of comparatively high speed and low power and transistors Q3 and Q4 are of comparatively low speed and high power.
When transistors Q3 and Q4 are field effect transistors or bipolar transistors as described above, and, in particular, the circuit parameters are set so that the output currents of the transistors do not become completely zero even if the load current is zero. This is performed for the purpose of fast response when the load has suddenly changed. Accordingly, when the load current is zero in this way, the through current that flows through the two transistors is called the design through current.
Where load LD may have various type of impedance (passive or active) the aforementioned negative feedback loop may possibly be changed to a positive feedback loop to cause oscillation. Therefore, capacitors C1 and C2 are connected in parallel to resistances R3 and R4 and roll-off of the negative feedback loop is effected. When transistors Q3 and Q4 are power field effect transistors, the frequency characteristics of these power field effect transistors do not extend over a wide range. Then without capacitors C1 and C2, the actual power field effect transistors can simulate equivalents of wide-band field effect transistors with capacitors C1 and C2.
Although a structure like that of high output amplifier 10 described above is stable when the load current changes slowly, there is the possibility that a large through current that exceeds the expected design through current will be generated in transistors Q3 and Q4 when the load current changes suddenly (quickly). For example, there are cases in which a suitable load resistance is connected and in which the input voltage changes rapidly, i.e., more rapidly than the response speed of the aforementioned negative feedback loop. Further, when high output amplifier 10 is used in the device power source of an integrated circuit (IC) tester, there are cases in which the operating state of an IC that is connected as the load will change due to signals from the outside. For example, when there has been a change from the usual operating state to a standby state, the load current changes more rapidly than the response speed of the aforementioned negative feedback loop of high output amplifier 10.
In order to clearly understand problems this invention intends to solve, we should consider the case in which load current I2 flowing into the current source load LD changes alternately and rapidly between 0 and IL. When load current I2 is IL, said load current I2 flows out from terminal 2 to the load (current source load).
(a) A steady state in which the load current I2 is 0: The voltages of terminal 1 and terminal 2, although this is not essential, are supposed to be both zero(0) for the sake of convenience. The gate voltages of transistors Q3 and Q4 are close to the respective threshold voltages and the respective drain currents are at low levels to give a design through current. The voltages applied on resistances R7 and R8 are controlled according to the non-inverting input terminal voltages of amplifiers A1 and A2 that are set depending on resistances R4 and R5 which have low resistance levels, and resistances R3 and R6 which are the collector resistances to the transistors Q1 and Q2.
(b) A state in which load current I2 changes rapidly from 0 to IL: At first, transistors Q3 and Q4 are not essentially operated, the emitter voltage of transistor Q1 is decreased and load current I2 is supplied from transistor Q1. The voltage across resistance R3 begins to rise accompanying the charging of capacitor C1 by the collector current of transistor Q1. The emitter voltage of transistor Q2 falls and transistor is essentially cut off, the voltage across resistance R6 begins to decrease at a time constant of R6*C2 then transistor Q4 goes off.
(c-1) A case in which load current I2 abruptly changes instantaneously from 0 to IL, after that the constant value IL of I2 is maintained: The current from transistor Q3 to terminal 2 is increased as the voltage across resistance R3 rises. Consequently, the current that is supplied from transistor Q1 to the load LD decreases and the rise of the voltage across resistance R3 is slowed down. The voltage of terminal 2 gradually rises, then the sum of the emitter current of transistor Q1 and the drain current of transistor Q3 becomes equal to load current I2(IL) to be stabilized When the level IL of load current I2 is high, it is designed so that the drain current of transistor Q3 accounts for most of load current I2.
(c-2) A case in which load current I2 changes instantaneously from 0 to IL, maintains a constant value of IL for a short time then returns to 0: This case differs from the case (c-1) and a through current flows through transistors Q3 and Q4 as below described.
The current from transistor Q3 to terminal 2 is increased as the voltage across resistance R3 rises. Consequently, the current from transistor Q1 to load LD decreases and the rise in the voltage across resistance R3 is slowed down. The voltage of the terminal 2 gradually rises and the sum of the emitter current of transistor Q1 and the drain current of transistor Q3, as load transistor Q2 remains off, becomes equal to load current I2 and stabilized. When the IL level of load current I2 is high, it is designed so that the drain current of transistor Q3 accounts for most of load current I2.
Then, when load current I2 returns to 0, the current flowing out from transistor Q3 causes the voltage of the terminal 2 to rise, transistor Q1 is cut off, transistor Q2 is turned on, current flows into the transistor Q2 and the voltage of the non-inverting input terminal of amplifier A2 is raised. As the voltage of said non-inverting input terminal rises, transistor Q4 is turned on and current is drawn from the terminal 2. Consequently, a through current that passes through transistor Q3 and transistor Q4 is generated. Because discharge of capacitor C1 does not occur rapidly, the through current persists for some time.
(d) From the state (c-2) described above up to the state in which load current I2 again assumes the level IL after a short time and then returns to 0: The voltages across capacitors C1 and C2 are greater than those in the case (a), a larger through current flows into transistors Q3 and Q4. Consequently, when the load current again assumes the level IL, the current from transistor Q3 becomes approximately the sum of the through current and load current I2. There is very slight discharge of capacitor C2 during the period that load current I2 assumes the value IL. Thus, when load current I2 goes to 0, increase of the voltage across capacitor C2 causes a further increase in the through current.
As should be clear from the foregoing description, when process (d) described above is repeated, the through current gradually increases. This through current is not extracted to the outside as load current I2, causing an increase in the internally power consumption of transistors Q3 and Q4. When the internally consumed power is low, no particular problems occur. However, in high power devices, it reaches several tens of W to several hundred of W. In extreme cases, transistors Q3 and Q4 themselves may be destroyed. Even when this does not happen, operation of transistors Q3 and Q4 becomes unstable since the operation is not performed at the operating point initially designed.
Consequently, the object of this invention is to provide a stable high output amplifier with which increases exceeding the design through current of the through current are controlled and which results in low internally power consumption.
The high output amplifier of this invention for the purpose of solving the aforementioned problems is equipped with a comparison amplifier in which the set voltage is received in the input of one side, a voltage of the output side is returned to the input of the other side and that generates output in response to the difference between the voltage of the aforementioned voltage of one side and the voltage of the aforementioned voltage of the other side, a low-pass filtering device that receives the output of the comparison amplifier, and that performs low-pass filtering of the output of the aforementioned comparison amplifier and outputs it, conversion devices that convert the output of said low-pass filtering device to complementary signals and push-pull output devices that supply electrical current for loading and that are driven by said complementary signals for outputting the voltage of the aforementioned output side, an increase in the through current of the aforementioned push-pull output device being decreased by changes in the aforementioned load due to the aforementioned low-pass filtering device. Consequently, a high output amplifier that is stable and consumes low power internally.
In the high output amplifier of this invention, the aforementioned comparison amplifier may be a complementary amplifier that generates complementary output and in that the aforementioned low-pass filtering device connects the complementary output of the aforementioned comparison amplifier and subjects it to low-pass filtering. When this is done, both of the complementary outputs of the complementary amplifier are used. Therefore, the response of the push-pull output stage is further accelerated when there is an abrupt change in load current.
The high output amplifier of this invention may be equipped with a buffer that receives the voltage set by the aforementioned comparison amplifier in the input of one side and with a resistance element that connects the output of said buffer with the input of the aforementioned other side so that the aforementioned voltage output can be obtained from the aforementioned resistance element. When this is done, a simple structure can be achieved whereby changes in the load current are detected directly and high-speed response can be effected.
In the high output amplifier of this invention, an integrating-type adder amplifier may be used as the low-pass filtering device. When it is constructed in this way, the frequency characteristics of the feedback circuit can be determined solely by adjustment of the integrating adder-type amplifier. Consequently, the driving of the push-pull output stage can be set so that the through current is increased.
Further, the aforementioned conversion device can be constructed so that it performs a low-pass filtering action for differing complementary signals that are output. By this means, variations in the response characteristics of the elements of the push-pull output stage can be regulated. Consequently, a high output amplifier with which there is little increase in through current at higher speeds can be obtained.
As described above, because the high output amplifier of this invention is stable in the presence of variations of load current, it is particularly suited for use with an IC tester so that the aforementioned push-pull output stage supplies current to the device to be tested by the IC tester.